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Intelligent AccessTM Voice Solutions
Am79D2251
Dual Intelligent Subscriber Line Audio-Processing Circuit (ISLAC)
DISTINCTIVE CHARACTERISTICS
s High performance digital signal processor provides programmable control of all major linecard functions -- 32 and 24 kb/s ADPCM to G726, as well as A-law/-law and linear codec -- Transmit and receive gain -- Two-wire AC impedance -- Transhybrid balance -- Equalization -- DC loop feeding -- Smooth or abrupt polarity reversal -- Loop supervision -- Off-hook debounce circuit -- Ground-key and ring-trip filters -- Ringing generation and control -- Adaptive hybrid balance -- Line and circuit testing -- Tone generation -- Metering generation at 12 kHz and 16 kHz -- Envelope shaping and level control s Selectable PCM/MPI or GCI digital interfaces -- Supports most available master clock frequencies from 512 kHz to 8.196 MHz s 0 to 70C commercial operation -- -40C to 85C extended temperature range available s +3.3 V DC operation s Exceeds LSSGR and ITU requirements s Supports external ringing with on-chip ring-trip circuit -- Automatic or manual ring-trip modes s DTMF detection according to Q.24 s 2100 Hz modem tone detection according to V.25
BLOCK DIAGRAM
A1
ISLIC
7 4 LD1 VREF
VCCA VCCD DGND1
B1 RC Networks and Protection A2
7 3 AGND1
DGND2
AGND2
TSCA/G
P1-P3
ISLIC
LD2
DRA/DD DXA/DU DCLK/S0 PCLK/FS
B2
RREF
Dual ISLAC
5
Ring-Trip Sense Resistors
5
MCLK
RSHB
BATH
RSLB
FS/DCL CS/RST DIO/S1
BATL
RSPB
BATP
INT
Pub. # 22829 Rev: C Amendment: /0 Issue Date: December 1999
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Distinctive Characteristics of The Intelligent AccessTM Voice chipset . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Linecard Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Intelligent AccessTM Voice Chipsets Environmental Ranges . . . . . . . . . . . . . . . . . . . . 14 Electrical Maximum Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Intelligent AccessTM Voice Chipsets System Target Specifications . . . . . . . . . . . . . . . . . . . 15 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Transmission and Signaling Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Transmit and Receive Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Attenuation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Group Delay Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Gain Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Total Distortion Including Quantizing Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Discrimination against Out-of-Band Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Spurious Out-of-Band Signals at the Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PCM Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCM Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 GCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 GCI Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision A to Revision B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision B to Revision C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Am79D2251
The dual ISLAC device, in combination with an ISLICTM device, implements a two channel universal telephone line interface. This enables the design of a single, low cost, high performance, fully software programmable line interface for multiple country applications worldwide. All AC, DC, and signaling parameters are fully programmable via microprocessor or GCI interfaces. Additionally, the dual ISLAC device has integrated self-test and line-test capabilities to resolve faults to the line or line circuit. The integrated test capability is crucial for remote applications where dedicated test hardware is not cost effective.
DISTINCTIVE CHARACTERISTICS OF THE INTELLIGENT ACCESSTM VOICE CHIPSET
s Performs all battery feed, ringing, signaling, hybrid and test (BORSCHT) functions s Two chip solution supports high density, multichannel architecture s Single hardware design meets multiple country requirements through software programming of: -- Ringing waveform and frequency -- DC loop-feed characteristics and current-limit -- Loop-supervision detection thresholds -- Off-hook debounce circuit -- Ground-key and ring-trip filters -- Off-hook detect de-bounce interval -- Two-wire AC impedance -- Transhybrid balance -- Transmit and receive gains -- Equalization -- Digital I/O pins -- A-law/-law and linear selection s Supports internal and external battery-backed ringing -- Self-contained ringing generation and control -- Supports external ringing generator and ring relay -- Ring relay operation synchronized to zero crossings of ringing voltage and current -- Integrated ring-trip filter and software enabled manual or automatic ring-trip mode s Supports metering generation with envelope shaping s Smooth or abrupt polarity reversal s Adaptive transhybrid balance -- Continuous or adapt and freeze s Supports both loop-start and ground-start signaling s Exceeds LSSGR and CCITT central office requirements s Selectable PCM or GCI interface -- Supports most available master clock frequencies from 512 kHz to 8.192 MHz s On-hook transmission s Power/service denial mode s Line-feed characteristics independent of battery voltage s Only 5 V, 3.3 V and battery supplies needed s Low idle-power per line s Linear power-feed with intelligent powermanagement feature s Compatible with inexpensive protection networks; Accommodates low-tolerance fuse resistors while maintaining longitudinal balance s Monitors two-wire interface voltages and currents for subscriber line diagnostics s Built-in voice-path test modes s Power-cross, fault, and foreign voltage detection s Integrated line-test features -- Leakage -- Line and ringer capacitance -- Loop resistance s Integrated self-test features -- Echo gain, distortion, and noise s 0 to 70C commercial operation -- -40C to 85C extended temperature range available s Small physical size s Up to three relay drivers per ISLICTM device -- Configurable as test load switches
Am79D2251
3
Figure 1. Dual ISLAC Block Diagram
IREF VHL1 VLB1 VOUT1 VINI1 VSAB1 VIMT1 VILG1 XSB1 Ch 1 Converter Block VREF MCLK FS/DCL PCLK/FS
Clock and Reference Circuits
PCM and GCI Interface and Time Slot Assigner
DXA/DU DRA/DD TSCA/G
VHL2 VLB2 VOUT2 VINI2 VSAB2 VIMT2 VILG2 XSB2 LD1 ISLIC Control Logic LD2 P1 P2 P3 Common External Sense Inputs XSC SHB SLB SPB Ch 2 Converter Block Digital Signal Processor GCI Control Logic and Microprocessor Interface DCLK/S0 DIO/S1 CS/RST INT
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Am79D2251
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The ordering number (valid combination) is formed by a combination of the elements below. Two ISLIC devices need to be used with this part.
Am79D2251 J C
TEMPERATURE RANGE C= Commercial (0C to +70C)
PACKAGE TYPE J = 44-pin plastic leaded chip carrier (PL044) V = 44-pin thin plastic quad flat pack (PQT044)
DEVICE NAME/DESCRIPTION Am79D2251 Advanced Dual Intelligent Subscriber Line AudioProcessing Circuit Valid Combinations Valid Combinations Am79D2251 Am79D2251 JC VC Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, and to check on newly released valid combinations.
Am79D2251
5
CONNECTION DIAGRAMS
Figure 2. 44-Pin PLCC Connection Diagram
VIMT2 VIMT1
40
VREF
VLB2 XSB2
XSB1
42
6
5
4
3
2
1
44
43
VLB1
41
IREF
SHB
XSC
SLB
AGND1 VILG2 VSAB2 VCCA2 VHL2 VIN2 VOUT2 SPB DGND1 LD2 P3
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36
AGND2 VILG1 VSAB1 VCCA1 VHL1 VIN1 VOUT1 DGND2 LD1
CS/RST
Dual ISLAC 44-Pin PLCC
35 34 33 32 31 30 29
DCLK/S0
18
19 20
21
22
23
24
25
26
27
28
P2
P1
MCLK
VCCD
DRA/DD
DXA/DU
Figure 3. 44-Pin TQFP Connection Diagram
VIMT2 VIMT1
34 33 32 31 30
PCLK/FS
VREF
XSB2
XSB1
36
VLB2
44
43
42
41
40
39
38
37
VLB1
35
IREF
XSC
SHB
SLB
TSCA/G
FS/DCL
DIO/S1
INT/S2
AGND1 VILG2 VSAB2 VCCA2 VHL2 VIN2 VOUT2 SPB DGND1 LD2 P3
1 2 3 4 5 6 7 8 9 10 11
AGND2 VILG1 VSAB1 VCCA1 VHL1 VIN1 VOUT1 DGND2 LD1
CS/RST
Dual ISLAC 44-Pin TQFP
29 28 27 26 25 24 23
DCLK/S0
12
13
14
15
16
17
18
19
20
21
22
INT/S2
PCLK/FS
DRA/DD
DXA/DU
TSCA/G
MCLK
P1
VCCD
6
Am79D2251
FS/DCL
DIO/S1
P2
PIN DESCRIPTIONS
Pin
AGND1, AGND2 DCLK/S0 DGND1- DGND2 DIO/S1
Pin Name
Analog Ground Data Clock/GCI Address Strap 0 Digital Ground Data I/O/GCI Address Strap 1
I/O O I
Analog circuitry ground returns
Description
Provides data control for MPI interface control. For GCI operation, this pin is device address bit 0. 5 V tolerant. Digital ground returns
I/O
For PCM backplane operation, control data is serially written into and read out of the ISLAC device via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate. DIO is high impedance except when data is being transmitted from the ISLAC device under control of CS/RST. For GCI operation, this pin is device address bit 1. 5 V tolerant. For the PCM highway, the receive PCM data is input serially through the DRA ports. The data input is received every 125 s and is shifted in, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. The receive port can receive information for direct control of the ISLIC device. This mode is selected in Device Configuration Register 2 (RTSEN = 1, RTSMD = 1). When selected, this data is received in an independently programmable timeslot from the PCM data. For the GCI mode, downstream receive and control data is accepted on this pin. 5 V tolerant. For the PCM highway, the transmit PCM data is transmitted serially through the DXA port. The transmission data output is available every 125 s and is shifted out, MSB first, in 8-bit PCM or 16-bit linear bursts at the PCLK rate. DXA is high impedance between bursts and while the device is in the inactive mode. Can also select a mode (RTSEN = 1, RTSMD = 1 or 0 in Device Configuration Register 2) that transmits the Signaling Register MSB contents first, in an independently programmable timeslot from the PCM data. This data is transmitted in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is transferred on this pin. 5 V tolerant. For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an 8 kHz Frame Sync signal on this pin in conjunction with the PCLK on the PCLK/FS pin (see below). This 8 kHz pulse identifies the beginning of a frame. The ISLAC device references individual timeslots with respect to this input, which must be synchronized to PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this pin in conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the rate at which data is shifted into or out of the PCM ports is a derivative of this DCL clock as selected in Device Configuration Register 1. 5 V tolerant. For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to interrupt a higher level processor. Several registers work together to control operation of the interrupt: Signaling and Global Interrupt Registers with their associated Mask Registers, and the Interrupt Register. See the description at configuration register 6 (Mask) for operation. Logic drive is selectable between open drain and TTL-compatible outputs. The S2 function is only available on the dual ISLAC device. For GCI operation, it is the device address bit 2. External resistor (RREF) connected between this pin and analog ground generates an accurate, on-chip reference current for the A/D's and D/A's on the ISLAC chip. The LD pins output 3-level voltages. When LDn is a logic 0, the destination of the code on P1-P3 is the relay control latches in the ISLIC control register. When LDn is a logic 1, the destination of P1-P3 is the mode control latches. LDn is driven to VREF when the contents of the ISLIC control register must not change. For PCM backplane operation, a DSP master clock connects here. A signal is required only for PCM backplane operation when PCLK is not used as the master clock. MCLK can be a wide variety of frequencies. Upon initialization the MCLK input is disabled, and relevant circuitry is driven by a connection to PCLK. The MCLK connection may be re-established under user control. 5 V tolerant. For PCM operation, this is PCM Clock. PCM operation is selected by the presence of a PCLK signal on this pin in conjunction with the FS on the FS/DCL pin (see below). For PCM backplane operation, connect a data clock, which determines the rate at which PCM data is serially shifted into or out of the PCM ports. PCLK can be any multiple of the FS frequency. The minimum clock frequency for linear/ companded data plus signaling data is 256 kHz. For GCI operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse that identifies the beginning of a frame. The ISLAC device references individual timeslots with respect to this input, which must be synchronized to DCL. 5 V tolerant. Control the operating modes of the two ISLIC devices connected to the dual ISLAC device.
DRA/DD
RX Path A Backplane Data/ GCI data Downstream, Receive Path B backplane data
I
DXA/DU
TX Path A Backplane Data/GCI Data Upstream, TX Path B Backplane Data
O
FS/DCL
Frame sync/GCI Downstream Clock
I
INT/S2
Interrupt/GCI Address Strap 2
O
IREF LD1-LD2
Current Reference Register Load
I O
MCLK
Master Clock
I
PCLK/FS
PCM Clock/Frame Sync
I
P1-P3
ISLIC Control
O
Am79D2251
7
Pin
CS/RST
Pin Name
Chip Select/Reset
I/O I
Description
For PCM backplane operation, a logic low on this pin for 15 or more DCLK cycles resets the sequential logic in the ISLAC device into a known mode. A logic low placed on this pin for less than 15 DCLK cycles is a chip select and enables serial data transmission into or out of the DIO port. For GCI operation, a logic low on this pin--for 1 ms or longer--resets the sequential logic into a known mode. See Table 2-4 in the Technical Reference for details. 5 V tolerant. Resistors that sense the high, low and positive battery voltages connect here. If only one negative battery is used, connect both resistors at the supply. If the positive battery is not used, leave the pin unconnected. These pins are current inputs whose voltage is held at VREF. For PCM backplane operation, TSCA is active low when PCM data is output on the DXA pin. The outputs are open-drain and are normally inactive (high impedance). Pull-up loads should be connected to VCCD. When GCI mode is selected, one of two GCI modes may be selected by connecting TSCA/G to DGND or VCCD. Connect to the VSAB pins of two ISLIC devices. +3.3 VDC supplies to the analog sections in each of the two channels. +3.3 VDC supply to all digital sections.
SHB, SLB, SPB
Battery Sense
I
TSCA/G,
Timeslot Control A/GCI Mode, Time Slot Control B Loop voltage sense Power Supply Power Supply Analog Reference High Level D/A TX Analog
O (PCM) I (GCI) I
VSAB1- VSAB2 VCCA1- VCCA2 VCCD VREF VHL1- VHL2 VIN1- VIN2 VLB1- VLB2
O O I
This pin provides a 1.4 V, single-ended reference to the two ISLIC devices to which the ISLAC device is connected. High-level loop control voltages on these pins are used to control DC-feed, internal ringing, metering and polarity reversal for each ISLIC device. Analog transmit signals (VTX) from each ISLIC device connect to these pins. The ISLAC device converts these signals to digital words and processes them. After processing, they are multiplexed into serial time slots and sent out of the DXA/DU pin. Normally connected to VCCA internally. They supply longitudinal reference voltages to the ISLIC devices during certain test procedures. These outputs are connected internally to VCCA during ISLIC Active, Standby, Ringing, and Disconnect modes. During test modes, it can be connected to the receive D/A. The IMT and ILG pins of two ISLIC devices connect to the VIMT1-VIMT4 and VILG1- VILG4 pins of the ISLAC chip. These pins are voltage inputs referenced to VREF. They require external resistors connected between each pin and VREF to convert IMTn and ILGn into voltages. The ISLAC device extracts and processes voice data from time slots on DRA/DD serial data port. After processing, the ISLAC device converts the voice data to analog signals that are sent out of these pins to each respective ISLIC device. External resistors connect here that sense an external voltage. In a linecard with external ringing, they are used to sense the voltage at the line side of the ring-feed resistor. These pins are current inputs whose voltage is held at VREF. An internal resistor converts currents flowing in these pins into voltages to be sampled by the A/D. An external resistor connects here that senses a common reference for external voltages sensed by resistors connected to XSB1-XSB4. This pin is a current input whose voltage is held at VREF. An internal resistor converts current flowing in this pin into a voltage to be sampled by the A/D. This pin is intended for sensing external ringer supply voltages. However, it can also be used to sense other test points when internal ringing is used.
Longitudinal Reference
O
VIMT1- VIMT2, VILG1- VILG2 VOUT1- VOUT2 XSB1- XSB2
Sense
I
RX Analog
O
External Sense
I
XSC
Common External Sense
I
8
Am79D2251
GENERAL DESCRIPTION
The Intelligent Access voice chipsets integrate all functions of the subscriber line for two subscriber lines. One or more of two chip types are used to implement the linecard; an ISLIC device and a dual ISLAC device. These provide the following basic functions: 1. The ISLIC device: A high voltage, bipolar IC that drives the subscriber line, maintains longitudinal balance and senses line conditions. 2. The dual ISLAC device: A low voltage CMOS IC that provides conversion and DSP functions for 2 channels. Complete schematics of linecards using the Intelligent Access voice chipsets for internal and external ringing are shown in Figure 4 and Figure 5. The ISLIC device uses reliable, bipolar technology to provide the power necessary to drive a wide variety of subscriber lines. It can be programmed by the ISLAC device to operate in eight different modes that control power consumption and signaling modes. This enables it to have full control over the subscriber loop. The ISLIC device is customized to be used exclusively with the ISLAC device as part of a multiple-line chipset. The ISLIC device requires only +5 V power and the battery supplies for its operation. The ISLIC device implements a linear loop-current feeding method with the enhancement of intelligent thermal management in a controlled manner. This limits the amount of power dissipated on the ISLIC chip by dissipating excess power in external resistors. Each ISLAC device contains high-performance codec circuits that provide A/D and D/A conversion for voice (codec), DC-feed and supervision signals for two subscriber channels. The ISLAC device contains a DSP core that handles signaling, DC-feed, supervision and line diagnostics for both channels. The DSP core selectively interfaces with three types of backplanes: s Standard PCM/MPI s Standard GCI s Modified GCI with a single analog line per GCI channel The Intelligent Access voice chipset provides a complete software configurable solution to the BORSCHT functions as well as complete programmable control over subscriber line DC-feed characteristics, such as current limit and feed resistance. In addition, these chipsets provide system level solutions for the loop supervisory functions and metering. In total, they provide a programmable solution that can satisfy worldwide linecard requirements by software configuration. Software programmed filter coefficients, DC-feed data and supervision data are easily calculated with the WinSLAC software. This PC software is provided free of charge. It allows the designer to enter a description of system requirements. WinSLAC then computes the necessary coefficients and plots the predicted system results. The ISLIC interface unit inside the ISLAC device processes information regarding the line voltages, loop currents and battery voltage levels. These inputs allow the ISLAC device to place several key ISLIC performance parameters under software control.
Am79D2251
9
The main functions that can be observed and/or controlled through the ISLAC backplane interface are: s DC-feed characteristics s Ground-key detection s Off-hook detection s DTMF detection s Modem tone (2100 Hz) detection s Metering signal s Longitudinal operating point s Subscriber line voltage and currents s Ring-trip detection s Abrupt and smooth battery reversal s Subscriber line matching s Ringing generation s Sophisticated line and circuit tests To accomplish these functions, the ISLIC device collects the following information and feeds it, in analog form, to the ISLAC device: s The metallic (IMT) and longitudinal (ILG) loop currents s The AC (VTX) and DC (VSAB) loop voltage The outputs supplied by the ISLAC device to the ISLIC device are then: s A voltage (VHLi) that provides control for the following high-level ISLIC device outputs: --DC loop current --Internal ringing signal --12 or 16 kHz metering signal s A low-level voltage proportional to the voice signal (VOUTi) s A voltage that controls longitudinal offset for test purposes (VLBi) The ISLAC device performs the codec and filter functions associated with the four-wire section of the subscriber line circuitry in a digital switch. These functions involve converting an analog voice signal into digital PCM samples and converting digital PCM samples back into an analog signal. During conversion, digital filters are used to band-limit the voice signals. The user-programmable filters set the receive and transmit gain, perform the transhybrid balancing function, permit adjustment of the two-wire termination impedance and provide frequency attenuation adjustment (equalization) of the receive and transmit paths. Adaptive transhybrid balancing is also included. All programmable digital filter coefficients can be calculated using WinSLAC software. The PCM codes can be either 16-bit linear two's-complement or 8-bit companded A-law or -law, with the further option of 32 or 24 kb/s ADPCM compression. Besides the codec functions, the Intelligent Access voice chipset provides all the sensing, feedback, and clocking necessary to completely control ISLIC device functions with programmable parameters. System-level parameters under programmable control include active loop current limits, feed resistance, and feed mode voltages. The ISLAC device supplies complete mode control to the ISLIC device using the control bus (P1-P3) and tri-level load signal (LDi). The Intelligent Access voice chipset provides extensive loop supervision capability including off-hook, DTMF, ring-trip and ground-key detection. Detection thresholds for these functions are programmable. A programmable debounce timer is available that eliminates false detection due to contact bounce. For subscriber line diagnostics, AC and DC line conditions can be monitored using built in test tools. Measured parameters can be compared to programmed threshold levels to set a pass/fail bit. The user can choose to send the actual PCM measurement data directly to a higher level processor by way of the voice channel. Both longitudinal and metallic resistance and capacitance can be measured, which allows leakage resistance, line capacitance, and telephones to be identified.
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Am79D2251
Figure 4. Internal Ringing Linecard Schematic
+5 V RSAi SA A RFAi AD VCC 3.3 V CREF RSN RHLai CHLbi RHLbi RRXi VOUTi DGND
VHLi RHLci RTESTMi U3 D1 RTi CADi VSAB CHPi BATH DT1i VTX U4 D2 CSSi B RFBi BD VLB RSBi SB CBDi TMS RMGPi DT2i*** TMP RLGi TMN VREF RMGLi ILG U1 Am79R241 RMTi VREF VILGi U2 ISLAC BACK PLANE IMT VLBi VIMTi HPB VINi CS HPA VSABi RHLdi CHLdi AGND
VREF VCCA VCCD VCC +3.3VDC
DHi BATH DLi BATL VBL VBH
VREF
VREF
LD GND CBATHi CBATLi P1 P2 RSVD RYE R2
RTESTLi
LDi
SPB
P1 P2 P3
SLB RSLB SHB RSHB IREF RREF
BATL BATH
P3
R3 R1 * CSS required for > 2.2 Vrms metering ** Connections shown for one channel *** DT2i diode is optional - should be connected if there is a chance that this chip may be replaced by Am79R251. BGND RSVD
Am79D2251
11
Figure 5. External Ringing Linecard Schematic
+5 V RSAi VCC SA 3.3 V CREF RSN RHLai A RFAi 1
KRi(A)
RRXi VOUTi DGND RHLbi AGND
8
AD
CHLbi
VHLi
CADi
RHLci RTi
RHLdi CHLdi VCCA
RTESTMi
6 7
U5 VSAB
VREF VCC +3.3 VDC
VSABi VINi
VCCD
2 DT1i BATH CS
CHPi
HPA
VTX
HPB CSSi B RFBi VLB 4 5
CBDi
VLBi VIMTi RMTi
BD
IMT
KRi (B)
RSBi SB TMS U1 Am79231
VREF ILG VILGi U2 ISLAC RLGi
DT2i***
RMGPi TMP VREF TMN RMGLi VREF
BACK PLANE
VREF
DHi BATH DLi BATL VBL VBH
LD GND P1 P2
LDi
P1 P2 P3 SPB SLB RSLB BATL BATH RSHB IREF RREF
CBATHi
CBATLi
P3
RSVD2 RYE R2H
RTESTLi
SHB
R3H
RGFDLi
R1 KRi +5 V BGND RSVD XSBi XSC
Ring Bus
* CSS required for > 2.2 Vrms metering ** Connections shown for one channel *** DT2i is optional - Should be put if there is a chance that this chip may be replaced by Am79R251. RSRBi
RSRC
12
Am79D2251
LINECARD PARTS LIST
The following list defines the parts and part values required to meet target specification limits for channel i of the linecard (i = 1, 2)
Item U1 U2 U3, U4 U5 D1, D2 DHi, DLi, DT1i, DT2i RFAi, RFBi RSAi, RSBi RTi RRXi RREF RMGLi, RMGPi RSHB, RSLB RHLai RHLbi RHLci RHLdi CHLbi CHLdi RMTi RLGi RTESTMi RTESTLi CADi, CBDi 1 CBATHi, CBATLi CHPi CSi
1 4
Type Am79R241
Value
Tol.
Rating ISLIC device
Comments
Am79X22xx
P1001SC TISP61089 Diode Diode Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Capacitor Capacitor Resistor Resistor Resistor Resistor Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Resistor 1A 100 mA 50 200 k 80.6 k 100 k 69.8 k 1 k 750 k 40.2 k 4.32 k 2.87 k 2.87 k 3.3 nF 0.82 F 3.01 k 6.04 k 2 k 2 k 22 nF 100 nF 22 nF 100 nF 56 pF 510 750 k 2% 2% 1% 1% 1% 5% 1% 1% 1% 1% 1% 10 % 10 % 1% 1% 1% 1% 10% 20% 20% 20% 5% 2% 2% 100 V 80 V 100 V 100 V 2W 1/4 W 1/8 W 1/8 W 1/8 W 1W 1/8 W 1/10 W 1/10 W 1/10 W 1/10 W 10 V 10 V 1/8 W 1/8 W 1W 1W 100 V 100 V 100 V 100 V 100 V 2W 1/4 W
ISLAC device
TECCOR Battrax protector Transient Voltage Suppresser, Power Innovations 50 ns Fusible PTC protection resistors Sense resistors
Current reference Thermal management resistors
Not Polarized Ceramic
Metallic test Longitudinal test Ceramic, not voltage sensitive Ceramic Ceramic Protector speed up capacitor Ceramic 1.2 W typ Matched to within 0.2% for initial tolerance and 0 to 70 C ambient temperature range.2 17 mW typ DPDT
CSSi3 RGFDi RSRBi, RSRc
Components for External Ringing
KRi
Relay
5 V Coil
Notes: 1. Value can be adjusted to suit application. 2. Can be looser for relaxed ring-trip requirements. 1% match (each resistor 1%) gives 1.275 mA uncertainty in ringing current sensing. 3. Required for metering > 2.5 Vrms, otherwise may be omitted. 4. DT2i is optional - Should be put if there is a chance that this chip may be replaced by Am79R251.
Am79D2251
13
ELECTRICAL CHARACTERISTICS Power Dissipation
Description Dual ISLAC Power Dissipation Test Conditions One channel activated All channels active All channels inactive Min Typ TBD TBD Max TBD TBD TBD mW Unit
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Storage Temperature Ambient Temperature, under Bias Ambient relative humidity (non condensing) VCCA with respect to DGND VCCD with respect to DGND VIN with respect to DGND 5 V tolerant pins AGND Latch up immunity (any pin) Any other pin with respect to DGND -60C TA +125C -40C TA +85C 5 to 100% -0.4 V to + 3.47 V -0.4 V to + 3.47 V -0.4 V to VCCA + 0.4 V -0.4 to Vcc + 2.25 or 5.25 V, whichever is less DGND 0.4 V 100 mA -0.4 V to VCC
Operating Ranges
Operating ranges define those limits over which the functionality of the device is guaranteed by 100 percent production testing. Specifications outside of the 0 to 70C range (-40 to 85C) are guaranteed through characterization and sample-lot testing production devices at the temperature extremes. Intelligent AccessTM Voice Chipsets Environmental Ranges
Ambient Temperature Ambient Relative Humidity -40 to +85C Commercial 15 to 85%
Electrical Maximum Ranges
Analog Supply VCCA Digital Supply VCCD DGND AGND +3.3 V 5% +3.3 V 5% 0V DGND 50 mV
14
Am79D2251
PERFORMANCE SPECIFICATIONS
The performance targets defined in this section are for the entire linecard comprised of both chips in the Intelligent Access voice chipsets unless otherwise noted. Specifications for the individual chips in the set will be published separately (see note 1). TA = 0 to 70C unless otherwise noted.
Intelligent AccessTM Voice Chipsets System Target Specifications
Item Peak Ringing Voltage Condition Active Ringing mode, RLOAD = 1500 , VBH = 80 V Active Ringing mode, Dual ISLAC generating internal ringing Active Ringing mode, RLOAD = 1500 , VBH = 80 V, ISLAC generating internal sinusoidal ringing Loop open, in anti-sat f = 50 Hz f = 200 to 3400 Hz 2 12 Min Typ 70 Max Unit V Note
Output Impedance during internal ringing Sinusoidal Ringing THD
200
2
%
PSRR (VBH, VBL)
dB
1, 2
Notes: 1. Not tested or partially-tested in production. 2. These numbers are only valid when an ISLIC device operates with an ISLAC device, because the ISLAC generates the anti-sat feed characteristic. When the Intelligent Access voice chipsets operate in the normal feed region, the performance is controlled by the ISLIC device. See appropriate ISLIC data sheet for specific PSRR.
Am79D2251
15
DC Specifications
No. 1 2 4 Item Input Low Voltage, All other digital inputs Input High Voltage, All other digital inputs Input Leakage Current All digital inputs except MCLK MCLK Input hysteresis (PCLK/FS, FS/DCL, MCLK, DIO, DRA) Ternary output voltages, LD1-2 High voltage Low voltage Output current Output Low Voltage (DXA/DU, DIO, INT, TSCA) Output Low Voltage (INT, TSCA) Output High Voltage (All digital outputs except INT in open drain mode and TSCA) Input Leakage Current (VIN1-2, VSAB1-2, VILG1-2, VIMT1-2) Input Leakage Current ( VSAB1-2) Input voltage (VIN1-2) -law A-law Input Voltage (VSAB 1-2 or VIMT1-2 or VILG1-2) Offset voltage allowed on VIN1-2 VHL output offset voltage VOUT1-2 offset Voltage Output voltage, VREF Capacitance load on VREF or VOUT1-2 Output drive current, VOUT1-2 or VLB1-2 Output leakage current VOUT1-2 or VLB1-2 Maximum output voltage on VOUT VLB1-2 operating voltage Maximum output voltage on VHL (KRFB) Gain from VSAB to VHL Gain from VSAB to VHL % error of VLB voltage (For VLB equation, see Am79R2xx/ Am79D2251 Technical Reference) Capacitance load on VLB1-2 Source or Sink -1 TBD |VOUT-VREF| with peak digital input Source current < 250 A or sink current < 25 A. |VHL-VREF| with peak digital input VFD = 1 VFD = 0 0.99 VREF -1.02 0.97 4.9 -0.0255 -5 1.00 5
-0.025
Condition
Min -0.05 -0.50 2.36 2.0 -10 -120 0.15
Typ
Max 1.36 V 0.80 V Vcc+0.4 5.25 +10 +180
Unit
Note
V
A
5 6
0.225
0.3
V
2
Iout = 200 A Iout = 2 mA Mid level Iol = 2 mA Iol = 10 mA Ioh = 400 A
VCC-0.45 -- -10
-- 0.4 +10 0.4 1.0
V V A
7 8 9
V VCC-0.4
10 11 12
TBD TBD 3.205 dBm0 3.14 dBm0 to insertion loss in ADC |Vov-VREF| where Vov is input overload voltage
A A
13 14 15 16 17 18 19 20 21 22 23 24 25 26
VREF -1.02 0.99 -50
1.02
VREF +1.02 1.05 +50 +40 +80
V
DISN off DISN on Load current = 0 to 10 mA Source or Sink
-40 -80 1.4
mV
9
V 200 +1 pF mA mA 1.05 VREF +1.02 1.03 5.1 -0.0245 +5 V 9 2 2
1.02
V V/V V/V %
9
27
120
pF
5
16
Am79D2251
No. 28
Item Capacitance load on XSB1-2, XSC
Condition
Min
Typ
Max 400
Unit pF
Note 5
Transmission and Signaling Specifications
Table 1. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
Signal at Digital Interface A-law digital mW or equivalent (0 dBm0) -law digital mW or equivalent (0 dBm0) 5,800 peak linear coded sine wave Transmit 0.5026 0.4987 0.5026 Receive 0.5026 0.4987 0.5025 Vrms Unit
No. 1
Item Insertion Loss
Condition Input: 1014Hz, -10dBm0 RG = AR = AX = GR = GX = 0 dB, AISN, R, X, B and Z filters disabled
Min
Typ
Max
Unit
Note
A-D D-A A-D + D-A A-D + D-A 2 3 Level set error (Error between setting and actual value) DR to DX gain in full digital loopback mode Idle Channel Noise, Psophometric Weighted (A-law)
-0.25 Temperature = 70C Variation over temperature A-D AX + GX D-A AR + GR DR Input: 1014 Hz, -10 dBm0 RG=AR=AX=GR=GX=0 dB, DISN, R, X, B and Z filters disabled Off-hook and On-hook AX = 0dB AR = 0dB A-D (PCM output) D-A (VOUT) Off-hook and On-hook AX = 0dB AR = 0dB A-D (PCM output) D-A (VOUT) A-D, Input signal = 0V 0 GX < 12 dB -12 GR 0 dB Input: 4.8 to 7.8 kHz, 200 mV p-p Measure 8000 Hz-Input frequency A-D D-A Gdisn = 0.9375 Vin = 0 dBm0 Gdisn = -0.9375 to 0.9375 1014 Hz; -10 dBmO B = Z = 0; X = R = 1 0 dBm0 0 dBm0 300 Hz to 3400 Hz 300 Hz to 3400 Hz -7 -0.25 -0.15 -0.1 -0.1 -0.3
0 0 0 0
+0.25 +0.25 +0.015 +0.1 0.1 +0.3 dB 6
4
dBm0p -69 -78
11
5
Idle Channel Noise, C Message weighted (-law)
dBrnC0 +19 +12 +7 0.1 0.1 dB 37 37 -0.25 +0.25 525 dB S 2 13, 12, 5 Bits 5 5 5 5 11
6 7 8 9
Coder Offset decision value, Xn GX step size GR step size PSRR (VCC) Image frequency
10 11
DISN gain accuracy End-to-end group delay
12
Crosstalk same channel
TX to RX RX to TX
-75 -75
dBm0
Am79D2251
17
No. 13
Item Crosstalk between channels TX or RX to TX TX or RX to RX 0 dBm0
Condition 1014 Hz 1014 Hz
Min
Typ
Max -76 -78
Unit dBm0
Note
Notes: 1. These tests are performed with the following load impedances: Frequency < 12 kHz - Longitudinal impedance = 500 ; metallic impedance = 300 Frequency > 12 kHz - Longitudinal impedance = 90 ; metallic impedance = 135 2. 3. 4. 5. 6. 7. Not tested or partially tested in production. This parameter is guaranteed by characterization or correlation to other tests. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. When the Intelligent Access voice chipset is in the anti-sat operating region, this parameter will be degraded. The exact degradation will depend on system design. Guaranteed by design. Overall 1.014 kHz insertion loss error of the Intelligent Access voice chipset is guaranteed to be 0.34 dB These SBAT, PSRR specifications are valid only when the ISLIC is used with the ISLAC, which generates the anti-sat reference. Since the anti-sat reference depends upon the battery voltage sensed by the VHB, VLB, and VPB pins of the ISLAC, the PSRR of the kit depends upon the amount of battery filtering provided by CB. Must meet at least one of these specifications. These voltages are referred to VREF These limits refer to the 2-wire output of an ideal ISLIC but reflect only the capabilities the ISLAC. When relative levels (dBm0) are used, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR + RG) from 0 to -12 dB. Group delay spec valid only when Channels 1-2 occupy consecutive slots in the frame. Programming channels in non-consecutive timeslots adds 1 frame delay in the Group delay measurements. The Group delay specification is defined as the sum of the minimum values of the group delays for transmit and the receive paths when the B, X, R, and Z filters are disabled with null coefficients. See Figure 15-3 for Group Delay Distortion. These limits reflect only the capabilities of the dual ISLAC device.
8. 9. 10. 11. 12. 13.
14.
18
Am79D2251
Transmit and Receive Paths
In this section, the transmit path is defined as the analog input to the ISLAC device (VINn) to the PCM voice output of the ISLAC A-law/ law speech compressor (See Figure 7-1 in the Am79R2xx/ Am79D2251x Technical Reference). The receive path is defined as the PCM voice input to the ISLAC speech expander to the analog output of the ISLAC device (VOUTn). All limits defined in this section are tested with B = 0, Z = 0 and X = R = RG = 1. When RG is enabled, a gain of -6.02 dB is added to the digital section of the receive path. When AR is enabled, a nominal gain of -6.02 dB is added to the analog section of the receive path. When AX is enabled, a nominal gain of +6.02 dB is added to the analog section of the transmit path. When relative levels (dBm0) are used in any of the following transmission characteristics, the specification holds for any setting of (AX + GX) gain from 0 to 12 dB or (AR + GR) from 0 to -12 dB. These transmission characteristics are valid for 0 to 70C.
Am79D2251
19
Attenuation Distortion
The attenuation of the signal in either path is nominally independent of the frequency. The deviations from nominal attenuation will stay within the limits shown in Figure 6. The reference frequency is 1014 Hz and the signal level is -10 dBm0. Figure 6. Transmit and Receive Path Attenuation vs. Frequency
2
Dual ISLAC Specification
1 Attenuation (dB)
0.80 0.65
0.6
0.2 0.125 0 -0.125
Receive path
0 200 300 600 3000 3200 3400 Frequency (Hz)
Minimum transmit attenuation at 60 Hz is 24 dB
Group Delay Distortion
For either transmission path, the group delay distortion is within the limits shown in Figure 7. The minimum value of the group delay is taken as the reference. The signal level should be -10 dBm0. Figure 7. Group Delay Distortion
420
Dual ISLAC Specification (Either Path)
Delay (S) 150
90
500
600
1000
2600
Frequency (Hz)
20
Am79D2251
2800
0
Single Frequency Distortion
The output signal level, at any single frequency in the range of 300 to 3400 Hz, other than that due to an applied 0 dBm0 sine wave signal with frequency f in the same frequency range, is less than -46 dBm0. With f swept between 0 to 300 Hz and 3.4 to 12 kHz, any generated output signals other than f are less than -28 dBm0. This specification is valid for either transmission path.
Intermodulation Distortion
Two sine wave signals of different frequencies, f1 and f2 (not harmonically related) in the range 300 to 3400 Hz and of equal levels in the range -4 to -21 dBm0, do not produce 2 * f1 - f2 products having a level greater than -42 dB, relative to the level of the two input signals. A sine wave signal in the frequency band 300 to 3400 Hz with input level -9 dBm0 and a 50 Hz signal with input level -23 dBm0 does not produce intermodulation products exceeding a level of -56 dBm0. These specifications are valid for either transmission path.
Am79D2251
21
Gain Linearity
The gain deviation relative to the gain at -10 dBm0 is within the limits shown in Figure 8 (A-law) and Figure 9 (-law) for either transmission path when the input is a sine wave signal of 1014 Hz. Figure 8. A-law Gain Linearity with Tone Input (Both Paths)
1.5
Dual ISLAC Specification
0.55 0.25 Gain (dB) 0 -55 -50 -0.25 -0.55 -40 -10 0 +3 Input Level (dBm0)
-1.5
Figure 9. -law Gain Linearity with Tone Input (Both Paths)
1.4
Dual ISLAC Specification
0.45 0.25 Gain (dB) 0 -55 -50 -0.25 -0.45 -37 -10 0 +3 Input Level (dBm0)
-1.4
22
Am79D2251
Total Distortion Including Quantizing Distortion
The signal to total distortion ratio will exceed the limits shown in Figure 10 for either path when the input signal is a sine wave signal of frequency 1014 Hz. Figure 10. Total Distortion with Tone Input, Both Paths
Dual ISLAC Specification
B A A B C D A-Law 35.5dB 35.5dB 30dB 25dB -Law 35.5dB 35.5dB 31dB 27dB
C D
Signal-to-Total Distortion (dB)
-45
-40
-30 Input Level (dBm0)
0
Overload Compression
Figure 11 shows the acceptable region of operation for input signal levels above the reference input power (0 dBm0). The conditions for this figure are: (1) 1 dB < GX +12 dB; (2) -12 dB GR < -1 dB; (3) Digital voice output connected to digital voice input; and (4) measurement analog to analog. Figure 11. A/A Overload Compression
9 8 7 6 Fundamental Output Power (dBm0) 5 4 3 2.6 2 1
Acceptable Region
1
2
3
4
5
6
7
8
9
Fundamental Input Power (dBm0)
Am79D2251
23
Discrimination against Out-of-Band Input Signals
When an out-of-band sine wave signal with frequency and level A is applied to the analog input, there may be frequency components below 4 kHz at the digital output which are caused by the out-of-band signal. These components are at least the specified dB level below the level of a signal at the same output originating from a 1014 Hz sine wave signal with a level of A dBm0 also applied to the analog input. The minimum specifications are shown in the following table.
Frequency of Out-of-Band Signal 16.6 Hz < f < 45 Hz 45 Hz < f < 65 Hz 65 Hz < f < 100 Hz 3400 Hz < f < 4600 Hz 4600 Hz < f < 100 kHz Amplitude of Out-of-Band Signal -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 -25 dBm0 < A 0 dBm0 Level below A 18 dB 25 dB 10 dB see Figure 12 32 dB
0 ISLAC Device Specification -10
-20 Level (dB) -30 -32 dB, -25 dBm0 < input < 0 dBm0 -40 -50 -28 dBm
3.4
4.0
4.6
19256A-012
Frequency (kHz) Note: The attenuation of the waveform below amplitude A between 3400 Hz and 4600 Hz is given by the formula:
( 4000 - f) Attenuation (db) = 14 - 14 sin ------------------------1200
Figure 12. Discrimination Against Out-of-Band Signals
24
Am79D2251
Spurious Out-of-Band Signals at the Analog Output
With PCM code words representing a sine wave signal in the range of 300 Hz to 3400 Hz at a level of 0 dBm0 applied to the digital input, the level of the spurious out-of-band signals at the analog output is less than the limits shown below.
Frequency 4.6 kHz to 40 kHz 40 kHz to 240 kHz 240 kHz to 1 MHz
Level -32 dBm0 -46 dBm0 -36 dBm0
With code words representing any sine wave signal in the range 3.4 kHz to 4.0 kHz at a level of 0 dBm0 applied to the digital input, the level of the signals at the analog output are below the limits in Figure 13. The amplitude of the spurious out-of-band signals between 3400 Hz and 4600 Hz is given by the formula:
( f - 4000 ) A = - 14 - 14 sin --------------------------- dBm0 1200
0 ISLAC Device Specification -10
-20 Level (dBm0) -30 -40 -50 -28 dB -32 dB
3.4
4.0
4.6
19256A-013
Frequency (kHz)
Figure 13. Spurious Out-of-Band Signals
Am79D2251
25
SWITCHING CHARACTERISTICS PCM Switching Characteristics
Figure 14. PCM Switching Characteristics VCC = 3.3 V +5%, AGND = DGND = 0 V
TBD TBD TBD TBD TBD
TEST POINTS
TBD
Microprocessor Interface Min and max values are valid for all digital outputs with a 100 pF load, except DIO,DXA, INTL, and TSCA which are valid with 150 pF loads.
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tOCSS tOCSH tOCSL tOCSO tODD tODH tODOF tODC tRST Chip select setup time, Output mode Chip select hold time, Output mode Chip select pulse width, Output mode Chip select off time, output Mode Output data turn on delay Output data hold time Output data turn off delay Output data valid Reset pulse width 0 50 3 50 50 s 50 8tDCY ns 1, 6 30 tDCY-10 tDCH-20 Symbol tDCY tDCH tDCL tDCR tDCF tICSS tICSH tICSL tICSO tIDS tIDH Parameter Data clock period Data clock HIGH pulse width Data clock LOW pulse width Rise time of clock Fall time of clock Chip select setup time, Input mode Chip select hold time, Input mode Chip select pulse width, Input mode Chip select off time, Input mode Input data setup time Input data hold time 25 30 30 0 8tDCY 1, 6 5 Min 122 48 48 15 15 tDCY-10 tDCH-20 ns 1 1 Typ Max Unit Note
26
Am79D2251
PCM Interface
No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol tPCY tPCH tPCL tPCF tPCR tFSS tFSH tTSD tTSO tDXD tDXH tDXZ tDRS tDRH tFST Parameter PCM clock period PCM clock HIGH pulse width PCM clock LOW pulse width Fall time of clock Rise time of clock FS setup time FS hold time Delay to TSCA valid Delay to TSCA off PCM data output delay PCM data output hold time PCM data output delay to high-Z PCM data input setup time PCM data input hold time PCM or frame sync jitter time 30 50 5 5 5 5 10 25 5 -97 97 70 70 70 80 3 4 Min. 0.122 48 48 15 15 tPCY-30 Typ Max 7.8125 Unit s ns Note 2
Master Clock For 2.048 MHz 100 PPM, 4.096 MHz 100 PPM, or 8.192 MHz 100 PPM operation:
No. 37 Symbol tMCY Parameter Period: 2.048 MHz Period: 4.096 MHz Period: 8.192 MHz Rise time of clock Fall time of clock MCLK HIGH pulse width MCLK LOW pulse width 48 48 Min 488.23 244.11 122.05 Typ 488.28 244.14 122.07 Max 488.33 244.17 122.09 15 15 ns Unit No 2
38 39 40 41
tMCR tMCF tMCH tMCL
Notes: 1. DCLK may be stopped in the HIGH or LOW state indefinitely without loss of information. When CS makes a transition to the High state, the last byte received will be interpreted by the Microprocessor Interface logic. 2. The PCM clock (PCLK or MCLK) frequency must be an integer multiple of the frame sync (FS) frequency with an accuracy of 100 PPM. This allowance includes any jitter that may occur between the PCM signals (FS, PCLK) and MCLK. The actual PCLK rate is dependent on the number of channels allocated within a frame. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be used for standard U.S. transmission systems. TSCA is delayed from FS by a typical value of N * tPCY, where N is the value stored in the time/clock slot register. tTSO is defined as the time at which the output driver turns off. The actual delay time is dependent on the load circuitry. The maximum load capacitance on TSCA is 150 pF and the minimum pull-up resistance is 360 . The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last. The ISLAC device requires 2.0 s between SIO operations. If the MPI is being accessed while the MCLK (or PCLK if combined with MCLK) input is not active, a Chip Select Off time of 20 s is required when accessing coefficient RAM.
3. 4.
5. 6.
Am79D2251
27
PCM Switching Waveforms Figure 15. Master Clock Timing
37
41 V
IH
V
IL
40 38
39
Figure 16. Microprocessor Interface (Input Mode)
1 2 5 VIH DCLK VIL VIL VIH
3 7 9 4 CS 6
8
10 DIO Data Valid
11 Data Valid Data Valid
28
Am79D2251
Figure 17. Microprocessor Interface (Output Mode)
DCLK
VIH VIL
13 CS 15
14 16
20 17 DIO Three-State
VOH Data Valid V
OL
18
19
Data Valid Data Valid
Three-State
Figure 18. PCM Highway Timing for XE = 0 (Transmit on Negative PCLK Edge))
Time Slot Zero, Clock Slot Zero 27 26 VIH PCLK VIL 24 28 FS 30 29 TSCA See Note 4 23 22 25
31 32 VOH DXA First Bit VOL 34 VIH DRA First Bit Second Bit VIL 35 33
Am79D2251
29
Figure 19. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)
Time Slot Zero, Clock Slot Zero 27 26 VIH PCLK VIL 24 23 22 25
FS 28 29 TSCA 30
See Note 4
31 VOH DXA First Bit VOL 34
32 33
35 VIH
DRA
First Bit
Second Bit VIL
GCI Timing Specifications
Symbol tR, tF tDCL tWH, tWL tR, tF tSF tHF tWFH tDDC tDDF tSD tHD Signal DCL DCL DCL FS FS FS FS DU DU DD DD Parameter Rise/fall time Period, FDCL = 2048 kHz FDCL = 4096 kHz Pulse width Rise/fall time Setup time Hold time High pulse width Delay from DCL edge Delay from FS edge Data setup Data hold twH+20 50 70 50 130 100 150 478 239 90 60 tDCL-50 ns Min Typ Max 60 498 249 Unit
Notes: 1. The Data Clock (DCL) can be stopped in the high or low state without loss of information. 2. A temporary stoppage of DCL must not put the ISLAC into a state in which it does not respond to a software reset command. 3. All frequency-dependent specifications are guaranteed for clock frequencies within 100 PPM from nominal.
30
Am79D2251
GCI Waveforms
DCL
FS
BIT 7
BIT 6
DD, DU
DETAIL A
tr
tf
DCL**
tWH
tDCL
tWL
FS
tSF
tHF
tWFH tDDF
DU
tDDC tSD tHD
DD
** Timing diagram valid for FDCL = 2048 or 4096 KHz
Am79D2251
31
PHYSICAL DIMENSIONS 44-Pin PLCC
.685 .695 .650 .656 .042 .056 .062 .083
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 DA78 6-28-94 ae
44-Pin TQFP
44
1
11.80 12.20 9.80 10.20
9.80 10.20 11.80 12.20
11 - 13 0.95 1.05 1.20 MAX
16-038-PQT-2 PQT 44 7-11-95 ae
1.00 REF.
0.30 0.45
0.80 BSC
11 - 13
32
Am79D2251
REVISION SUMMARY Revision A to Revision B * Revision A was a condensed version of the datasheet while Revision B contains the full version. Revision B to Revision C * Page 13, Linecard Parts List, Rows CHLbi and CHLdi: switched the numbers in the "Values" column.
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice.
(c) 1999 Advanced Micro Devices, Inc. All rights reserved.
Trademarks AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. Intelligent Access and WinSLAC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am79D2251
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